As semiconductor devices are increasing in layout density, technology scaling has led to development of fin-based, also referred to as FinFET structures as an alternative to bulk metal-oxide-semiconductor FET structures for improved scalability. The FinFET utilizes a semiconductor fin to wrap the conducting channel, and the fin forms the body of the transistor. In effect, the gate electrode of the transistor straddles or surrounds the fin. During operation, current flows between the source and drain terminals along the gated sidewall surfaces of the fin.
It has been recognized that many integrated circuit designs require both low operating voltage FETs for their ability to operate at high frequencies, and high operating voltage FETs for their ability to interface with high voltage signals of auxiliary devices. As such, FET devices include a lateral disposition of a core well (e.g., for low operating voltages) and an input/output (I/O) well (e.g., for high operating voltages). As the technology in lateral disposition moves to 7 nm and beyond, the shallow trench isolation quality worsens due to lower temperature annealing, resulting in worse hot carrier injection that leads to larger drive current degradation stemming from the elevated density of interference states.